library ieee;
use ieee.std_logic_1164.all;

entity adder1 is
	port(
	a,b,cin : in std_logic;
	cout,sum  : out std_logic
	);
end;

architecture behave of adder1 is

component h_adder
port(
		a,b : in std_logic;
		co,sum : out std_logic
		);
END COMPONENT;

signal P,Q : std_logic;
signal or2a,or2b : std_logic;
begin
	process(or2a,or2b,a,b) begin
		cout <= or2a or or2b;
		sum  <= P;
	end process;

A1 : h_adder port map(a=>a,b=>b,co=>or2a,sum=>Q);
A2 : h_adder port map(a=>Q,b=>cin,co=>or2b,sum=>P);
end behave;
